This invention relates generally to ternary logic integrated circuits and more particularly to such logic circuits utilizing N-channel or P-channel depletion devices along with complementary MOS devices.
In the development and improvement of intergrated circuit semiconductor devices, a constant objective has been and continues to be that of reducing the overall area on a so-called semiconductor "chip" required for a circuit. Heretofore, this objective included attempts to improve fabrication processes as well as the internal arrangements of the individual circuit elements. The application of ternary, or three level logic circuitry, has been considered as affording at least a partial solution to the problem of minimizing circuit area because it created the possibility of using more efficient interconnections within a circuit. For example, in a ternary system, each data line could carry three possible pieces of information rather than two and the control lines could carry two possible pieces of control information rather than one. Thus, the area required for data and control lines could be substantially reduced.
The multivalued logic circuits previously considered by those versed in the art may be found in IEEE Transactions on Computers, vol. c 30, No. 9, September 1981, p. 619, "The Prospects for Multivalued Logic: A Technology and Applications View", by K. C. Smith. The multivalued logic circuits disclosed in the aforesaid article, at most, transform three separate ternary input values into either three separate ternary output values where one such value is equal to the input value causing it or two separate ternary output values out of a possible set of three values or into a pair of binary output values. Saturated N-channel enhancement devices with appropriately large thresholds were used to create the "one" logic value and these may also be used with the present invention. However, in the aforesaid prior art circuits, there were only two ternary levels of outputs out of a possible three or a pair of binary outputs or where there were three ternary outputs, one equalled the input causing it. This provided only limited utility for complete ternary logic and/or simply transformed ternary signals into binary signals to communicate with the binary world and to compute in binary to get back to ternary in the end. The present invention provides much greater flexibility of complete ternary logic circuit, wherein each input value may go into a different output value and all three ternary levels may be obtained as outputs on a circuit. Also included in the prior art are numerous patents which utilize variations of multivalued circuit inputs or outputs, such as two binary inputs and three voltage supplies (shown in U.S. Pat. No. 3,949,242), or a single input converter with three output states, one of which is of high impedance and not active (shown in U.S. Pat. No. 4,217,502), or a tristate driver circuit wherein the third state is high impedance and not active (shown in U.S. Pat. Nos. 4,280,065; 4,037,114 and 4,029,971). Despite the aforesaid prior activity, applicant is unaware of any disclosure wherein three-level logic inputs produce three-level active logic outputs, where each output is different in logic value than the input logic value causing it, in an integrated circuit device.
It is, therefore a general object of the present invention to provide such a logic circuit with a three-level input and output which is adaptable for implementation as an integrated semiconductor device naturally imbedded into a mixed (i.e., including N or P-channel depletion devices) CMOS technology.
Another object of the invention is to provide a three-level logic circuit as a building block for integrated systems that have a substantially smaller area and package pin count than a comparable device using convention two-level logic.
Yet another object of the invention is to provide a three-level logic circuit that enables each data line to carry three pieces of information and each control line to carry two pieces of information, threreby allowing the area on an integrated circuit "chip" that is normally required for data and control lines to be reduced.
Still another object of the invention is to provide a three-level logic circuit wherein each input value to the circuit results in an output with another logic value and all three levels are achieved as outputs.